Reduction of development time and system engineering costs

Imaging and machine-vision systems development requires tremendous effort and resources.
Final development and testing of such systems are done on site. This methodology forces companies to develop complex and expensive intelligent machines and to plan intricate field testing accordingly.
Moreover, it is extremely difficult to detect and to analyze rare occurring bugs.

A unique technology known as PROC_CamSim™ enables the users to perform most of the development at a low cost quiet lab environment. Thus, this new technology improves significantly the productivity and reduces the overall expenses of vision and imaging systems development.

PROC_CamSim™ data flow repetition capability ensures that algorithms are validated and work as expected with the relevant input. Moreover, once a rare occurring bug is detected, it’s respective data flow can be accurately reconstructed to locate the bug and fix it quickly.

Developers that are require a customized simulator regardless of whether it is only a camera, a machine or a system simulation. The PROC_CamSim™ simplifies tremendously the simulation process by enabling the user to add FPGA code, to connect to the system IOs and to add a user process to handle the additional tasks of the simulator.
An additional application driver is automatically generated by the PROCWizard, a GiDEL provided development kit.

The PROC_CamSim™ system consists of the CamSim host-based software application, an FPGA board, and CameraLink™ driver daughter board.

Key Features

• Simulates all Camera Link v1.1 configurations (base / medium / full)
• Flexible to meet user's demands
• Machine simulator capability by adding user IOs
• Supports AVI videos and BMP, JPG, PNG images and RAW image/video files.
• Internal HW fixed-pattern generator.
• Fully programmable video timing and data parameters with an easy-to-use GUI
• User-configurable camera control (CC) lines for triggering options.
• Outputs 1-8 pixel channels simultaneously at 20-85 MHz according to CameraLink™ v1.1 specifications.
• Software and FPGA customization for extended machine simulation and/or custom logic/processes.
• Up to 2GB image buffer.
• Two MDR-26 connectors interface for full mode Camera Link v1.1 configuration.

Host-based Software Application Automates Setup
The GUI-based CamSim Software provides a fast and easy way to configure the simulator to mimic any CameraLink™ camera and to output any image to the Grabber side.
The software configures all the simulation parameters, including timing and resolution, CameraLink channels structure, etc.. The application also provides the mechanism to decode and load AVI video or image data into the FPGA via the DMA channel and synchronize it with the hardware side. This video/image data can be used in addition to available static test patterns generated in hardware.

All-inclusive Hardware Speeds Implementation
The PROC_CamSim™ hardware consists of two elements. Primary processing power is provided by either a PCI based PROCSparkII system with CycloneII-35 FPGA and PCI bus interface, a PCIe x 4 Lanes PROCe60 system with Stratix II 60 FPGA or by a PCIe x 4 Lanes PROCe III with Stratix III 80E FPGA. The CameraLink physical layer interface and output to the system under development is provided by a PSDB_CL_OUT daughter board. The reconfigurable hardware generates valid signals at specified timing configuration, generates static test patterns, and restructures data corresponding to the CameraLink channel configuration, and sets up serial communication with the frame grabber.
The CamSim Software configures the programmable FPGA hardware to define the current configuration of the simulator including pixel bit depth, timing, taps, frame source, etc..
Customizability Expands Value. The system provides for customization by the development team. Users may develop their own software controller, based on an automatically generated PROC class, and thus build a custom software application to control the simulator. User can also implement their own custom FPGA designs based on a supplied template, insert their own configuration or control module in the FPGA design, and recompile to create their own simulator.
Adding an optional PSDB_IO module or using the on board available I/Os, extends the simulation IO interface to enable customization into a machine simulator.

Applications

• Vision algorithms development
• Image processing application testing
• Machine vision integration
• Vision system reliability testing.
• Debug of "rarely appearing bugs"

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